Automatic partitioning of signal processing programs for symmetric multiprocessors

Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE. One such application domain is on-board signal processing. The Strategic Defense Initiative Organization (SDIO) Signal and Data Processing Benchmark Suite [Nic91] is a set of kernels drawn from aerospace and military systems that perform functions such as radar and sonar signal processing. These kernels are CPU intensive. Because they have real-time scheduling demands, minimizing latency is critical. Traditionally, these applications run on custom-designed distributed-memory systems that have up to hundreds of processors operating in a coarse-grained data flow fashion, as illustrated in Figure 1. The application is usually partitioned by hand into stages that are spread across the processors. Code is generated separately for each processor and communication and synchronization among these processes is explicitly specified by the programmer. Frequently, the poor quality or unavailability of compilers for the specialized processors used requires hand-coding in assembly language. An alternative to this approach is to replace a large number of potentially specialized processors in these systems with a much smaller number of SMP systems. Projected trends in advanced CMOS technology indicate the availability of small-scale SMPs on a single chip or MCM at relatively low prices in the near future. It is inevitable that aerospace and military on-board signal processing systems will need to leverage the price/performance benefits of such commercial SMP systems. There is a crucial need for compilation tools that can take existing application software, possibly in the form of compiled object code, and partition and schedule it for efficient execution on such systems. Such tools will facilitate the porting of on-board signal processing sequential programs for parallel execution on these modern high-performance SMP systems. The specific focus of this paper is to investigate the feasibility of automatically parallelizing on-board signal and data processing applications for parallel execution on commercial SMPs. We present the PEDIGREE compiler, Figure 1. High-level view of typical on-board signal processing sensor-based image processing feature-based signal processing command and control data processing Abstract Symmetric multiprocessor systems are increasingly common , not only as servers, but as a vehicle for executing a single application in parallel in order to reduce its execution latency. This paper presents …